Dc converter

ABSTRACT

What is provided is a direct-current converter which improves unstableness of operations owing to an error of a bottom detection circuit and fluctuations of a detection point which are caused by disturbance. The direct-current converter includes a bottom detection circuit  13  which detects a minimum voltage of a main switch Q 1  after an auxiliary switch Q 2  is switched off, an ideal gate signal generation circuit  21  which generates an ideal gate signal for switching on the main switch Q 1  at a time of the minimum voltage of the main switch Q 1  based on an output of the bottom detection circuit  13 , a comparison circuit  22  which calculates an error output between the ideal gate signal generated by the ideal gate signal generation circuit  21  and an actual gate signal which switches on the main switch Q 1 , and a first delay circuit  14  which controls a delay of an ON time of the main switch Q 1  by the actual gate signal based on the error output of the comparison circuit  22 , thereby performing control to make the actual gate signal approach the ideal gate signal.

TECHNICAL FIELD

The present invention relates to a direct-current converter which ishigh-efficiency and low-noise.

BACKGROUND ART

FIG. 1 shows an example of a conventional direct-current converter(Japanese Patent Laid-Open Publication No. 2000-92829). Thedirect-current converter shown in FIG. 1 has a system called “activeclamp”. To a direct-current power supply Vin, a main switch Q1 formed ofa MOSFET (hereinafter, referred to as an FET) and the like is connectedthrough a primary winding P1 (winding number: n1) of a transformer T. Toboth ends of the primary winding P1, a series circuit composed of anauxiliary switch Q2 formed of a MOSFET (hereinafter, referred to as anFET) and the like and composed of a snubber capacitor C2 is connected.The main switch Q1 and the auxiliary switch Q2 are configured to bealternately switched on/off by PWM control of a control circuit 111.

Moreover, the primary winding P1 of the transformer T and a secondarywinding S1 of the transformer T are wound so as to generate a commonmode voltage to each other. To the secondary winding S1 (winding number:n2) of the transformer T, a rectifying/smoothing circuit composed ofdiodes D10 and D11, a reactor L10 and a capacitor C10 is connected. Therectifying/smoothing circuit rectifies and smoothes a voltage (a pulsevoltage of which ON/OFF is controlled) induced by the secondary windingS1 of the transformer T, and outputs a direct-current output to a load30.

Based on an output voltage of the load 30, the control circuit 111generates a control signal formed of a pulse for controlling the ON/OFFof the main switch Q1, and controls a duty ratio of the control signalso that the output voltage becomes a predetermined voltage. Moreover,the direct-current converter includes an inverter 112, a bottomdetection circuit 113, a first delay circuit 114, a second delay circuit115, a low-side driver 116, and a high-side driver 117.

The inverter 112 inverts a Q1 control signal Q1 c for the main switch Q1from the control circuit 111, and outputs the inverted Q1 control signalQ1 c to the second delay circuit 115. The bottom detection circuit 113detects the minimum voltage (hereinafter, referred to as a bottomdetection signal Btm) of the main switch Q1 after the auxiliary switchQ2 is switched off. The first delay circuit 114 generates a Q1 gatesignal Q1 g in which rising timing of a Q1 control signal Q1 c from thecontrol circuit 111 is delayed to rising timing of the bottom detectionsignal Btm from the bottom detection circuit 113, and outputs thegenerated Q1 gate signal Q1 g to the low-side driver 116. The low-sidedriver 116 applies the Q1 gate signal Q1 g from the first delay circuit114 to a gate of the main switch Q1, and drives the main switch Q1. Thesecond delay circuit 115 generates a Q2 gate signal Q2 g in which risingtiming of the Q2 control signal Q2 c for the auxiliary switch Q2, whichis inverted by the inverter 112, is delayed by a predetermined time, andoutputs the generated Q2 gate signal Q2 g to the high-side driver 117.The high-side driver 117 applies the Q2 gate signal Q2 g from the seconddelay circuit 115 to a gate of the auxiliary switch Q2, and drives theauxiliary switch Q2.

Next, operations of the direct-current converter thus configured will bedescribed while referring to a timing chart shown in FIG. 2. In FIG. 2,a voltage Q1 v between both ends of the main switch Q1 is shown.

First, when the Q1 control signal Q1 c from the control circuit 111rises to a H level at a time t31, the Q2 control signal Q2 c falls to aL level. Accordingly, the Q2 gate signal Q2 g falls to the L level, andtherefore, the auxiliary switch Q2 is switched off. Moreover, the bottomdetection signal Btm rises to the H level at the time t31.

Then, when the auxiliary switch Q2 is switched off, the voltage Q1 v ofthe main switch Q1 is decreased. At a time t32, the minimum value(bottom) of the voltage Q1 v is detected by the bottom detection circuit113. At this time, the bottom detection signal Btm from the bottomdetection circuit 113 falls to the L level.

Then, the Q1 gate signal Q1 g which rises to the H level at fallingtiming (time 32) of the bottom detection signal Btm from the bottomdetection circuit 113 is generated by the first delay circuit 114, andthe Q1 gate signal Q1 g is applied to the gate of the main switch Q1through the low-side driver 116. Accordingly, the main switch Q1 isswitched on. Specifically, a bottom-voltage switch or zero-voltageswitch of the main switch Q1 can be achieved.

When the main switch Q1 is switched on, a current flows to the mainswitch Q1 from the direct-current power supply Vin through the primarywinding P1 of the transformer T. At this time, the current flows througha cycle of the constituents S1, D10, L10, C10 and S1.

Next, when the main switch Q1 is switched off by the Q1 control signalQ1 c at a time t33, a parasitic capacitor (not shown) owned by the mainswitch Q1 is charged with energy stored in the primary winding P1 of thetransformer T and a leakage inductance between the primary and secondarywindings of the transformer T, a voltage resonance is formed, and thevoltage Q1 v of the main switch Q1 rises during a period from the timet33 to a time t34. Moreover, a current flows through a cycle of theconstituents L10, C10, D11 and L10, and supplied to a load R30.

Then, when the auxiliary switch Q2 is switched on by the Q2 gate signalQ2 g at the time t34, the energy stored in the primary winding P1 of thetransformer T is supplied to the capacitor C2, and the capacitor C2 ischarged therewith. Next, the energy stored in the capacitor C2 flowsthrough a cycle of the constituents C2, Q2, P1 and C2.

Note that, as a document of a related art of the conventionaldirect-current converter, for example, Japanese Patent Laid-OpenPublication No. H7-203688 (published in 1995) is mentioned.

DISCLOSURE OF THE INVENTION

As described above, in the conventional direct-current converter, theminimum value of the voltage of the main switch Q1 is detected by thebottom detection circuit 113 after the auxiliary switch Q2 is switchedoff, and the on-delay of the main switch Q1 is controlled so that the Q1gate signal Q1 g rises to the H level at the falling timing of thebottom detection signal Btm. Therefore, when a delay time of the mainswitch Q1 is varied owing to a detection error of the bottom detectioncircuit 113 and fluctuations of a detection point which are caused bydisturbance, the Q1 gate signal Q1 g of the main switch Q1 is varied.Accordingly, the operations of the direct-current converter become veryunstable.

Moreover, when there is a delay from the detection of the bottom to theswitch-on of the main switch Q1, the switch-on of the main switch Q1 isdelayed from the bottom. Accordingly, it has been necessary to configuresuch a circuit which reduces the delay from the detection of the bottomto the switch-on of the main switch Q1. Therefore, it has been necessaryto switch on the main switch Q1 at high speed, leading to a defect thatswitching noise is increased, and the like.

It is an object of the present invention to provide a direct-currentconverter which improves the unstableness of the operations owing to theerror of the bottom detection circuit and the fluctuations of thedetection point which are caused by the disturbance, is capable ofeliminating an influence of the delay from the detection of the bottomto the switch-on of the main switch, and capable of reducing theswitching noise.

In order to achieve the above-described object, the present invention isconfigured as follows. An invention of claim 1 is a direct-currentconverter which alternately switches on/off a main switch and anauxiliary switch, thereby rectifying and smoothing a voltage of asecondary winding of a transformer, thus obtaining a direct-currentoutput, the main switch being connected in series to a primary windingof the transformer, and the auxiliary switch being of a series circuitconnected to both ends of the primary winding of the transformer or bothends of the main switch and composed of a capacitor and the auxiliaryswitch, comprising: bottom detection means configured to detect aminimum voltage of the main switch after the auxiliary switch isswitched off; control signal generation means configured to generate anideal control signal which switches on the main switch at a time of theminimum voltage of the main switch based on an output of the bottomdetection means; error calculation means configured to calculate anerror output between the ideal control signal generated by the controlsignal generation means and an actual control signal which switches onthe main switch; and delay control means configured to control a delayof an ON time of the main switch by the actual control signal based onthe error output of the error calculation means, thereby performingcontrol to make the actual control signal approach the ideal controlsignal.

An invention of claim 2 is a direct-current converter which switcheson/off a main switch connected in series to a primary winding of atransformer, thereby rectifying and smoothing a voltage of a secondarywinding of the transformer, thus obtaining a direct-current output,comprising: bottom detection means configured to detect a minimumvoltage of the main switch when a voltage of the main switch isdecreased; control signal generation means configured to generate anideal control signal which switches on the main switch at a time of theminimum voltage of the main switch based on an output of the bottomdetection means; error calculation means configured to calculate anerror output between the ideal control signal generated by the controlsignal generation means and an actual control signal which switches onthe main switch; and delay control means configured to control a delayof an ON time of the main switch by the actual control signal based onthe error output of the error calculation means, thereby performingcontrol to make the actual control signal approach the ideal controlsignal.

An invention of claim 3 is the direct-current converter according to anyone of claims 1 and 2, further comprising: integration means configuredto integrate the error output of the error calculation means, whereinthe delay control means controls the delay of the ON time of the actualcontrol signal based on an integrated output of the integration means,thereby performing the control to make the actual control signalapproach the ideal control signal.

An invention of claim 4 is the direct-current converter according toclaim 3, wherein the delay control means comprises: a delay unit whichdelays a signal for switching on the main switch, the signal being fromthe control means, by a predetermined time by means of a charging timefor a delaying capacitor connected in series to a resistor; and avariable delay unit which applies a difference voltage between theintegrated output of the integration means and a reference voltage tothe delaying capacitor, thereby shortening the predetermined delay timein response to the difference voltage, and the delay control meansapplies the actual control signal to a control terminal of the mainswitch based on a voltage of the delaying capacitor.

An invention of claim 5 is the direct-current converter according to anyone of claims 1 to 4, wherein a direct-current power supply or arectified voltage unit which obtains a rectified voltage by rectifyingan alternating-current voltage of an AC power supply is connected toboth ends of a series circuit composed of the primary winding of thetransformer and the main switch.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a circuit diagram showing an example of a conventionaldirect-current converter.

FIG. 2 is a timing chart of signals of respective portions of theconventional direct-current converter.

FIG. 3 is a circuitry diagram showing a direct-current converteraccording to a first embodiment.

FIG. 4 is a timing chart of signals of respective portions during asteady state where an error between an ideal gate signal and an actualgate signal disappears in the direct-current converter according to thefirst embodiment.

FIG. 5 is a timing chart of signals of the respective portions during atransient state where the actual gate signal approaches the ideal gatesignal owing to the error between the ideal gate signal and the actualgate signal in the direct-current converter according to the firstembodiment.

FIG. 6 is a circuitry diagram showing a direct-current converteraccording to a second embodiment.

FIG. 7 is a view showing a truth table of a D-type flip-flop as an idealgate signal generation circuit in the direct-current converter accordingto the second embodiment.

FIG. 8 is a circuitry diagram showing a direct-current converteraccording to a third embodiment.

FIG. 9 is a timing chart of signals of respective portions during atransient state where an actual gate signal approaches an ideal gatesignal owing to an error between the ideal gate signal and the actualgate signal in the direct-current converter according to the thirdembodiment.

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiments of a direct-current converter according to the presentinvention will be described below in detail with reference to thedrawings.

FIRST EMBODIMENT

FIG. 3 is a circuitry diagram of a direct-current converter according toa first embodiment. In the direct-current converter shown in FIG. 3, amain switch Q1 and an auxiliary switch Q2 are configured to bealternately switched on/off by PWM control of a control circuit 11.Based on an output voltage of a load 30, the control circuit 11generates a control signal formed of a pulse for controlling ON/OFF ofthe main switch Q1, and controls a duty ratio of the control signal sothat the output voltage becomes a predetermined voltage.

Moreover, the direct-current converter includes an inverter 12, a bottomdetection circuit 13, a first delay circuit 14, a second delay circuit15, a low-side driver 16, a high-side driver 17, an ideal gate signalgeneration circuit 21, a comparison circuit 22, and an integrationcircuit 23.

The inverter 12 inverts a Q1 control signal Q1 c for the main switch Q1from the control circuit 11, and outputs the inverted Q2 control signalQ2 c to the second delay circuit 15. The bottom detection circuit 13detects the minimum voltage (hereinafter, referred to as a bottomdetection signal Btm) of the main switch Q1 after the auxiliary switchQ2 is switched off. The ideal gate signal generation circuit 21generates an ideal gate signal IGs based on the bottom detection signalBtm from the bottom detection circuit 13 and the Q1 control signal Q1 cfrom the control circuit 11.

The comparison circuit 22 compares the ideal gate signal IGs from theideal gate signal generation circuit 21 and an actual Q1 gate signal Q1g for driving the main switch Q1 with each other, and calculates anerror output Cop between the ideal gate signal IGs and the actual Q1gate signal Q1 g. The integration circuit 23 integrates the error outputCop from the comparison circuit 22, and outputs an integrated outputInt.

The first delay circuit 14 corresponds to delay control means of thepresent invention. The first delay circuit 14 receives the integratedoutput Int of the integration circuit 23 and the Q1 control signal Q1 cof the control circuit 11, and performs control to shorten a delay timefrom a rising time of the Q1 control signal Q1 c to a rising time of theQ1 gate signal Q1 g in response to a value of the integrated output Intfrom the integration circuit 23. Specifically, the first delay circuit14 controls the delay of the rising time (ON time) of the actual Q1 gatesignal Q1 g, thereby performing control to make the actual Q1 gatesignal Q1 g approach the ideal gate signal IGs.

The low-side driver 16 applies the Q1 gate signal Q1 g from the firstdelay circuit 14 to the gate of the main switch Q1, and drives the mainswitch Q1. The second delay circuit 15 generates a Q2 gate signal Q2 gin which rising timing of the Q2 control signal Q2 c for the auxiliaryswitch Q2, which is inverted by the inverter 12, is delayed by apredetermined time, and outputs the generated Q2 gate signal Q2 g to thehigh-side driver 17. The high-side driver 17 applies the Q2 gate signalQ2 g from the second delay circuit 15 to a gate of the auxiliary switchQ2, and drives the auxiliary switch Q2.

Note that, in FIG. 3, the same reference numerals are assigned to thesame portions as constituent portions shown in FIG. 1, and descriptionthereof is omitted.

Next, operations of the direct-current converter thus configured will bedescribed while referring to flowcharts shown in FIG. 4 and FIG. 5. FIG.4 is a timing chart of signals of the respective portions during asteady state where the error between the ideal gate signal and theactual gate signal disappears in the direct-current converter accordingto the first embodiment. FIG. 5 is a timing chart of signals of therespective portions during a transient state where the actual gatesignal approaches the ideal gate signal owing to the error between theideal gate signal and the actual gate signal in the direct-currentconverter according to the first embodiment. Note that FIG. 4 and FIG. 5show a voltage Q1 v between both ends of the main switch Q1.

First, when the Q1 control signal Q1 c from the control circuit 11 risesto a H level at a time t1, the Q2 control signal Q2 c falls to a Llevel. Accordingly, the Q2 gate signal Q2 g falls to the L level, andtherefore, the auxiliary switch Q2 is switched off. Moreover, the bottomdetection signal Btm rises to the H level at the time t1.

Then, when the auxiliary switch Q2 is switched off, the voltage Q1 v ofthe main switch Q1 is decreased. At a time t2, the minimum value(bottom) of the voltage Q1 v is detected by the bottom detection circuit13. At this time, the bottom detection signal Btm from the bottomdetection circuit 13 falls to the L level.

Then, the ideal gate signal IGs which rises to the H level at thefalling time t2 of the bottom detection signal Btm from the bottomdetection circuit 13 is generated by the ideal gate signal generationcircuit 21. Moreover, the error output Cop between the ideal gate signalIGs and the actual Q1 gate signal Q1 g is calculated by the comparisoncircuit 22. Specifically, as shown in FIG. 5, the error output Cop isformed of a pulse having a pulse width from a rising time (for example,time t2) of the ideal gate signal IGs to the rising time (for example,time t21) of the actual Q1 gate signal Q1 g.

Moreover, the error output Cop from the comparison circuit 22 isintegrated by the integration circuit 23, and accordingly, theintegrated output Int becomes a value directly proportional to amagnitude of the error output Cop. Next, the first delay circuit 14performs the control to shorten the delay time from the rising time ofthe Q1 control signal Q1 c to the rising time of the Q1 gate signal Q1 gin response to the value of the integrated output Int from theintegration circuit 23. For example, during a period from the time t2 tothe time t21, the integrated output Int is relatively large, andaccordingly, the control is performed to shorten a delay time DT1 fromthe rising time t1 of the Q1 control signal Q1 c to the rising time t21of the Q1 gate signal Q1 g. Therefore, at timing in the next cycle, thedelay time becomes a delay time DT2 from a rising time t5 of the Q1control signal Q1 c to a rising time t61 of the Q1 gate signal Q1 g.

Furthermore, at the next timing, the delay time becomes a delay time DT3from a rising time t9 of the Q1 control signal Q1 c to arising time t101of the Q1 gate signal Q1 g. Specifically, the control is performed forthe delay of the rising time (ON time) of the actual Q1 gate signal Q1g, and the actual Q1 gate signal Q1 g is made to approach the ideal gatesignal IGs. Moreover, when the difference between the actual Q1 gatesignal Q1 g and the ideal gate signal IGs disappears, the timing chartas shown in FIG. 4 appears.

Next, at the time t21, the Q1 gate signal Q1 g is applied to the gate ofthe main switch Q1 through the low-side driver 16, and accordingly, themain switch Q1 is switched on. Specifically, a bottom-voltage switch orzero-voltage switch of the main switch Q1 can be achieved.

When the main switch Q1 is switched on, a current flows from adirect-current power supply Vin to the main switch Q1 through theprimary winding P1 of the transformer T. At this time, the current flowsthrough a cycle of the constituents S1, D10, L10, C10, and S1.

Next, when the main switch Q1 is switched off by the Q1 control signalQ1 c at a time t3, a parasitic capacitor (not shown) owned by the mainswitch Q1 is charged with energy stored in the primary winding P1 of thetransformer T and a leakage inductance between the primary and secondarywindings of the transformer T, a voltage resonance is formed, and thevoltage Q1 v of the main switch Q1 rises during a period from the timet3 to a time t4. Moreover, a current flows through a cycle of theconstituents L10, C10, D11 and L10, and supplied to a load R30.

Moreover, the Q2 gate signal Q2 g in which the rising time of the Q2control signal Q2 c for the auxiliary switch Q2, which is inverted bythe inverter 12, is delayed by the predetermined time is generated bythe second delay circuit 15. At the time t4, the Q2 gate signal Q2 g isapplied to the gate of the auxiliary switch Q2 through the high-sidedriver 17, and switches on the auxiliary switch Q2. Therefore, theenergy stored in the primary winding P1 of the transformer T is suppliedto a capacitor C2, and the capacitor C2 is charged therewith. Next, theenergy stored in the capacitor C2 flows through a cycle of theconstituents C2, Q2, P1 and C2.

As described above, according to the direct-current converter accordingto the first embodiment, the error between the actual Q1 gate signal Q1g and the ideal gate signal IGs is integrated, and the control isperformed to make the actual Q1 gate signal Q1 g approach the ideal gatesignal IGs. In such a way, unstableness of the operations owing to anerror of the bottom detection circuit 13 and fluctuations of a detectionpoint which are caused by disturbance can be improved, and stableoperations can be obtained. Moreover, an influence of the delay from thedetection of the bottom to the generation of the Q1 gate signal Q1 g canbe eliminated, and accordingly, it is not necessary to switch on themain switch Q1 at high speed, and switching noise can be reduced.

SECOND EMBODIMENT

FIG. 6 is a circuitry diagram of a direct-current converter according toa second embodiment. The direct-current converter according to thesecond embodiment, which is shown in FIG. 6, provides a specific circuitexample of the direct-current converter according to the firstembodiment.

In the bottom detection circuit 13 shown in FIG. 6, a cathode of a diodeD1, one end of a resistor R1 and one end of a resistor R10 are connectedto a base of a transistor Q3, and an emitter of the transistor Q3 isconnected to an anode of the diode D1, and grounded. One end of aresistor R2 is connected to a collector of the transistor Q3, and theother end of the resistor R1 and the other end of the resistor R2 areconnected to a power supply Vcc. The other end of the resistor R10 isconnected to a drain of the main switch Q1 through a capacitor C1.

The ideal gate signal generation circuit 21 includes an inverter 211, aninverter 212, and a D-type flip-flop (DFF) 213. The inverter 211 invertsthe bottom detection signal Btm from the collector of the transistor Q3,and outputs the inverted bottom detection signal Btm to a clock terminalCL of the DFF 213. The inverter 212 inverts the Q1 control signal Q1 cfrom the control circuit 11, and outputs the inverted Q1 control signalQ1 c to a reset terminal R of the DFF 213. To a terminal D of the DFF213, the Q1 control signal Q1 c from the control circuit 11 is inputted,and a terminal S is grounded. A DFF output from a terminal Q isoutputted as the ideal gate signal IGs to the comparison circuit 22.

A truth table of the DFF 213 is shown in FIG. 7.

The comparison circuit 22 is formed of an exclusive-OR circuit (XOR)221, and the XOR 221 takes an exclusive OR of the DFF output from theDFF 213 and the actual Q1 gate signal Q1 g applied to the main switchQ1, and as the error output Cop, outputs the XOR output thus taken tothe integration circuit 23.

The integration circuit 23 is formed by connecting a resistor R3 and acapacitor C3 in series to each other. One end of the resistor R3 isconnected to an output of the XOR 221, one end of the capacitor C3 isgrounded, and the integrated output Int is outputted from a connectingpoint of the capacitor C3 and the resistor R3 to a noninvertingterminal + of an error amplifier 141 of the first delay circuit 14.

In the first delay circuit 14, a reference power supply Er is connectedto an inverting terminal—of the error amplifier 141, and an outputterminal of the error amplifier 141 is connected to an anode of a diodeD3 through a resistor R4. A cathode of the diode D3 is connected to oneend of a resistor R5 and one end of a capacitor C4, the other end of theresistor R5 is connected to the power supply Vcc, and the other end ofthe capacitor C4 is grounded. An output of the control circuit 11 isconnected to a cathode of a diode D2 through a buffer 142, and an anodeof the diode D2 is connected to the one end of the capacitor C4. Aconnecting point of the resistor R5 and the capacitor C4 is connected tothe gate of the main switch Q1 and an input terminal of the XOR 221through the low-side driver 16.

In the second delay circuit 15, an output of the inverter 12 isconnected to a cathode of a diode D4 through a buffer 151, an anode ofthe diode D4 is connected to one end of a capacitor C5 and one end of aresistor R6, the other end of the resistor R6 is connected to the powersupply Vcc, and the other end of the capacitor C5 is grounded. Aconnecting point of the resistor R6 and the capacitor C5 is connected tothe gate of the auxiliary switch Q2 through the high-side driver 17.

Next, operations of the direct-current converter according to the secondembodiment, which is thus configured, will be described.

First, when the Q1 control signal Q1 c from the control circuit 11 risesto the H level at the time t1, the Q2 control signal Q2 c falls to the Llevel. Accordingly, the Q2 gate signal Q2 g falls to the L level, andtherefore, the auxiliary switch Q2 is switched off.

Then, when the auxiliary switch Q2 is switched off, the voltage Q1 v ofthe main switch Q1 is decreased during the period from the time t1 to atime t2. At this time, in the bottom detection circuit 13, a currentflows through a route of the constituents D1, R10, C1, P1, Vin and GND,and the transistor Q3 is switched off. Therefore, the bottom detectionsignal Btm of the H level is outputted from the collector of thetransistor Q3 to the inverter 211 in the ideal gate signal generationcircuit 21. The bottom detection signal Btm is inverted by the inverter211, falls to the L level, and is inputted to the clock terminal CL ofthe DFF 213. Moreover, a signal of the L level is inputted to the resetterminal R of the DFF 213, and a signal of the H level is inputted tothe terminal D of the DFF 213. Therefore, the ideal gate signal IGs ofthe L level is outputted from the terminal Q of the DFF 213.

The XOR 221 takes an exclusive OR of the Q1 gate signal Q1 g of the Llevel, which is applied to the main switch Q1, and the ideal gate signalIGs of the L level from the terminal Q of the DFF 213, and outputs theerror output Cop of the L level to the one end of the resistor R3 of theintegration circuit 23.

Next, when discharge of the capacitor C1 is finished and at the time t2,the voltage Q1 v falls to the minimum value (bottom), a current flowsthrough a route of the constituents Vin, P1, C1, R10 and Q3, and thetransistor Q3 is switched on. Therefore, the minimum value (bottom) ofthe voltage Q1 v is detected by the bottom detection circuit 13. At thistime, the bottom detection signal Btm of the L level is outputted fromthe collector of the transistor Q3 to the inverter 211 in the ideal gatesignal generation circuit 21. The bottom detection signal Btm isinverted by the inverter 211, and the inverted bottom detection signalof the H level is inputted to the clock terminal CL of the DFF 213.Therefore, the ideal gate signal IGs of the H level is outputted fromthe terminal Q of the DFF 213.

Hence, during the period from the time t2 to the time t21, the XOR 221takes the exclusive OR of the Q1 gate signal Q1 g of the L level, whichis applied to the main switch Q1, and the ideal gate signal IGs of the Hlevel from the terminal Q of the DFF 213, and outputs the error outputCop of the H level to the one end of the resistor R3 of the integrationcircuit 23. Accordingly, the integrated output Int from the connectingpoint of the resistor R3 and the capacitor C3 rises to the high voltage,and is inputted to the noninverting terminal + of the error amplifier141, and therefore, a voltage in response to the value of the integratedoutput from the output of the error amplifier 141 is obtained.Therefore, by this voltage, a current flows through a route of theconstituents R4, D3 and C4. Specifically, in the capacitor C4, a totalcurrent of the current from the resistor R5 and the current from thediode D3 flows, and accordingly, a charging time for the capacitor C4 isshortened.

Specifically, the charging time for the capacitor C4 is shortened inresponse to the value of the integrated output Int from the integrationcircuit 23, and thus the delay time from the rising time of the Q1control signal Q1 c to the rising time of the Q1 gate signal Q1 g can beshortened. Hence, as already described with reference to the timingchart of FIG. 5, the control is performed for the delay of the risingtime (ON time) of the actual Q1 gate signal Q1 g, and thus the actual Q1gate signal Q1 g can approach the ideal gate signal IGs.

Next, at the time t21, the Q1 gate signal Q1 g is applied to the gate ofthe main switch Q1 through the low-side driver 16, and accordingly, themain switch Q1 is switched on. Specifically, the bottom-voltage switchor zero-voltage switch of the main switch Q1 can be achieved.

When the main switch Q1 is switched on, a current flows from thedirect-current power supply Vin to the main switch Q1 through theprimary winding P1 of the transformer T. At this time, the current flowsthrough a cycle of the constituents S1, D10, L10, C10 and S1.

Next, when the main switch Q1 is switched off by the Q1 control signalQ1 c at the time t3, the parasitic capacitor (not shown) owned by themain switch Q1 is charged with the energy stored in the primary windingP1 of the transformer T and the leakage inductance between the primaryand secondary windings of the transformer T, the voltage resonance isformed, and the voltage Q1 v of the main switch Q1 rises during a periodfrom the time t3 to the time t4. Moreover, the current flows through thecycle of the constituents L10, C10, D11 and L10, and supplied to theload R30.

Moreover, the Q2 control signal Q2 c of the H level is inputted to thecathode of the diode D4 through the buffer 151, and accordingly, thediode D4 enters a reverse biased state. Therefore, the current flowsfrom the power supply Vcc to the capacitor C5 through the resistor R6,and the capacitor C5 is charged therewith. Specifically, the Q2 gatesignal Q2 g in which the rising time is delayed by a delay timedetermined by a time constant of the resistor R6 and the capacitor C5 isgenerated by the second delay circuit 15.

Then, at the time t4, the Q2 gate signal Q2 g is applied to the gate ofthe auxiliary switch Q2 through the high-side driver 17, and switches onthe auxiliary switch Q2. Therefore, the energy stored in the primarywinding P1 of the transformer T is supplied to the capacitor C2, and thecapacitor C2 is charged therewith. Next, the energy stored in thecapacitor C2 flows through the cycle of the constituents C2, Q2, P1 andC2.

As described above, also in the direct-current converter according tothe second embodiment, a similar effect to the effect of thedirect-current converter according to the first embodiment is obtained.

THIRD EMBODIMENT

FIG. 8 is a circuitry diagram of a direct-current converter according toa third embodiment. The direct-current converter according to the thirdembodiment, which is shown in FIG. 8, is one which obtains adirect-current output by switching on/off the main switch. Thedirect-current converter according to the third embodiment ischaracterized in that the auxiliary switch Q2, the inverter 12, thesecond delay circuit 15, the high-side driver 17, the capacitor C2, thediode D11 and the reactor L10 are deleted from the configuration of thedirect-current converter according to the first embodiment, which isshown in FIG. 3. Moreover, the primary winding P1 and secondary windingS1 of the transformer T are wound in phases reverse to each other.

Other configurations shown in FIG. 8 are the same as the configurationsof the constituent portions shown in FIG. 3. The same reference numeralsare assigned to the same portions, and description thereof is omitted.

Next, operations of the direct-current converter according to the thirdembodiment, which is thus configured, will be described while referringto a timing chart shown in FIG. 9.

As seen from the timing chart shown in FIG. 9, schematically, the timingchart concerned is similar to the timing chart shown in FIG. 5 except aportion relating to the auxiliary switch Q2.

At the time t3, the main switch Q1 is switched off by the Q1 controlsignal. At this time, the parasitic capacitor (not shown) owned by themain switch Q1 is charged with excited energy induced by the primarywinding P1 of the transformer T, the voltage resonance is formed, andthe voltage Q1 v of the main switch Q1 rises during a period from thetime t3 to the time t4.

Moreover, the energy is transmitted to the secondary side through acycle of the constituents S1, D10, C10 and S1. When the energy inducedin the transformer T is emitted through the cycle of the constituentsS1, D10, C10 and S1 (when the transformer T is reset), the voltage Q1 vof the main switch Q1 is decreased.

As described above, also in the direct-current converter according tothe third embodiment, a similar effect to the effect of thedirect-current converter according to the first embodiment is obtained.

Note that, though the series circuit composed of the auxiliary switch Q2and the capacitor C2 is connected to both ends of the primary winding P1of the transformer T in the first and second embodiments, for example,the series circuit may also be connected to both ends of the main switchQ1.

Moreover, though the direct-current power supply Vin is connected to theseries circuit composed of the primary winding P1 of the transformer Tand the main switch Q1 in the first to third embodiments, for example, arectified voltage unit which obtains a rectified voltage by rectifyingan alternating-current voltage of an AC power supply may also beconnected to the series circuit concerned.

Furthermore, though only the parasitic capacitor is provided in the mainswitch Q1 in the first to third embodiments, another capacitor may alsobe connected to both ends of the main switch Q1.

INDUSTRIAL APPLICABILITY

According to the present invention, the unstableness of the operationsowing to the error of the bottom detection circuit and the fluctuationsof the detection point which are caused by the disturbance can beimproved, and the stable operations can be obtained. Moreover, theinfluence of the delay from the detection of the bottom to the switch-onof the main switch can be eliminated, and accordingly, it is notnecessary to switch on the main switch at high speed, and the switchingnoise can be reduced.

1. A direct-current converter which alternately switches on/off a mainswitch and an auxiliary switch, thereby rectifying and smoothing avoltage of a secondary winding of a transformer, thus obtaining adirect-current output, the main switch being connected in series to aprimary winding of the transformer, and the auxiliary switch being of aseries circuit connected to both ends of the primary winding of thetransformer or both ends of the main switch and composed of a capacitorand the auxiliary switch, comprising: bottom detection means configuredto detect a minimum voltage of the main switch after the auxiliaryswitch is switched off; control signal generation means configured togenerate an ideal control signal which switches on the main switch at atime of the minimum voltage of the main switch based on an output of thebottom detection means; error calculation means configured to calculatean error output between the ideal control signal generated by thecontrol signal generation means and an actual control signal whichswitches on the main switch; and delay control means configured tocontrol a delay of an ON time of the main switch by the actual controlsignal based on the error output of the error calculation means, therebyperforming control to make the actual control signal approach the idealcontrol signal.
 2. The direct-current converter according to claim 1,further comprising: integration means configured to integrate the erroroutput of the error calculation means, wherein the delay control meanscontrols the delay of the ON time of the actual control signal based onan integrated output of the integration means, thereby performing thecontrol to make the actual control signal approach the ideal controlsignal.
 3. The direct-current converter according to claim 2, whereinthe delay control means comprises: a delay unit which delays a signalswitching on the main switch, the signal being from the control means,by a predetermined time by means of a charging time for a delayingcapacitor connected in series to a resistor; and a variable delay unitwhich applies a difference voltage between the integrated output of theintegration means and a reference voltage to the delaying capacitor,thereby shortening the predetermined delay time in response to thedifference voltage, and the delay control means applies the actualcontrol signal to a control terminal of the main switch based on avoltage of the delaying capacitor.
 4. The direct-current converteraccording to claim 1, wherein a direct-current power supply or arectified voltage unit which obtains a rectified voltage by rectifyingan alternating-current voltage of an AC power supply is connected toboth ends of a series circuit composed of the primary winding of thetransformer and the main switch.
 5. A direct-current converter whichswitches on/off a main switch connected in series to a primary windingof a transformer, thereby rectifying and smoothing a voltage of asecondary winding of the transformer, thus obtaining a direct-currentoutput, comprising: bottom detection means configured to detect aminimum voltage of the main switch when a voltage of the main switch isdecreased; control signal generation means configured to generate anideal control signal which switches on the main switch at a time of theminimum voltage of the main switch based on an output of the bottomdetection means; error calculation means configured to calculate anerror output between the ideal control signal generated by the controlsignal generation means and an actual control signal which switches onthe main switch; and delay control means configured to control a delayof an ON time of the main switch by the actual control signal based onthe error output of the error calculation means, thereby performingcontrol to make the actual control signal approach the ideal controlsignal.
 6. The direct-current converter according to claim 5, furthercomprising: integration means configured to integrate the error outputof the error calculation means, wherein the delay control means controlsthe delay of the ON time of the actual control signal based on anintegrated output of the integration means, thereby performing thecontrol to make the actual control signal approach the ideal controlsignal.
 7. The direct-current converter according to claim 6, whereinthe delay control means comprises: a delay unit which delays a signalswitching on the main switch, the signal being from the control means,by a predetermined time by means of a charging time for a delayingcapacitor connected in series to a resistor; and a variable delay unitwhich applies a difference voltage between the integrated output of theintegration means and a reference voltage to the delaying capacitor,thereby shortening the predetermined delay time in response to thedifference voltage, and the delay control means applies the actualcontrol signal to a control terminal of the main switch based on avoltage of the delaying capacitor.
 8. The direct-current converteraccording to claim 5, wherein a direct-current power supply or arectified voltage unit which obtains a rectified voltage by rectifyingan alternating-current voltage of an AC power supply is connected toboth ends of a series circuit composed of the primary winding of thetransformer and the main switch.